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<a href="#define-members">Macros</a>  </div>
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<div class="title">xrtcpsu_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaf4ce7179e0fe961edf74c804ae1be55f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gaf4ce7179e0fe961edf74c804ae1be55f">XRTC_BASEADDR</a>&#160;&#160;&#160;0xFFA60000U</td></tr>
<tr class="memdesc:gaf4ce7179e0fe961edf74c804ae1be55f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Xrtc Base Address.  <a href="group__rtcpsu__v1__0.html#gaf4ce7179e0fe961edf74c804ae1be55f">More...</a><br /></td></tr>
<tr class="separator:gaf4ce7179e0fe961edf74c804ae1be55f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15fe16b0b19b172cc0b43af6c94698df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga15fe16b0b19b172cc0b43af6c94698df">XRTC_SET_TIME_WR_OFFSET</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga15fe16b0b19b172cc0b43af6c94698df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcSetTimeWr.  <a href="group__rtcpsu__v1__0.html#ga15fe16b0b19b172cc0b43af6c94698df">More...</a><br /></td></tr>
<tr class="separator:ga15fe16b0b19b172cc0b43af6c94698df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8aad0b4ff0c6c094abd427ca68bfb72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gae8aad0b4ff0c6c094abd427ca68bfb72">XRTC_SET_TIME_RD_OFFSET</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gae8aad0b4ff0c6c094abd427ca68bfb72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcSetTimeRd.  <a href="group__rtcpsu__v1__0.html#gae8aad0b4ff0c6c094abd427ca68bfb72">More...</a><br /></td></tr>
<tr class="separator:gae8aad0b4ff0c6c094abd427ca68bfb72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7226dae4931d57f6e45a86c0b1b8fa2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga7226dae4931d57f6e45a86c0b1b8fa2f">XRTC_CALIB_WR_OFFSET</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga7226dae4931d57f6e45a86c0b1b8fa2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcCalibWr.  <a href="group__rtcpsu__v1__0.html#ga7226dae4931d57f6e45a86c0b1b8fa2f">More...</a><br /></td></tr>
<tr class="separator:ga7226dae4931d57f6e45a86c0b1b8fa2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1370c975fd33563789e4a6737599668a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga1370c975fd33563789e4a6737599668a">XRTC_CALIB_RD_OFFSET</a>&#160;&#160;&#160;0x0000000CU</td></tr>
<tr class="memdesc:ga1370c975fd33563789e4a6737599668a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcCalibRd.  <a href="group__rtcpsu__v1__0.html#ga1370c975fd33563789e4a6737599668a">More...</a><br /></td></tr>
<tr class="separator:ga1370c975fd33563789e4a6737599668a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fa52cd698601011816bcb3a78cabc6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga7fa52cd698601011816bcb3a78cabc6a">XRTC_CUR_TIME_OFFSET</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga7fa52cd698601011816bcb3a78cabc6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcCurTime.  <a href="group__rtcpsu__v1__0.html#ga7fa52cd698601011816bcb3a78cabc6a">More...</a><br /></td></tr>
<tr class="separator:ga7fa52cd698601011816bcb3a78cabc6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4fcad14886e97664d39d03c875332cfc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga4fcad14886e97664d39d03c875332cfc">XRTC_CUR_TCK_OFFSET</a>&#160;&#160;&#160;0x00000014U</td></tr>
<tr class="memdesc:ga4fcad14886e97664d39d03c875332cfc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcCurTck.  <a href="group__rtcpsu__v1__0.html#ga4fcad14886e97664d39d03c875332cfc">More...</a><br /></td></tr>
<tr class="separator:ga4fcad14886e97664d39d03c875332cfc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaefe187edd9e6057a21bed63b21980824"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gaefe187edd9e6057a21bed63b21980824">XRTC_ALRM_OFFSET</a>&#160;&#160;&#160;0x00000018U</td></tr>
<tr class="memdesc:gaefe187edd9e6057a21bed63b21980824"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcAlrm.  <a href="group__rtcpsu__v1__0.html#gaefe187edd9e6057a21bed63b21980824">More...</a><br /></td></tr>
<tr class="separator:gaefe187edd9e6057a21bed63b21980824"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5031f5d32d26c4887751966503470c83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga5031f5d32d26c4887751966503470c83">XRTC_INT_STS_OFFSET</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga5031f5d32d26c4887751966503470c83"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcIntSts.  <a href="group__rtcpsu__v1__0.html#ga5031f5d32d26c4887751966503470c83">More...</a><br /></td></tr>
<tr class="separator:ga5031f5d32d26c4887751966503470c83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac915150ede3fb8aab0d68c1ed072e4f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gac915150ede3fb8aab0d68c1ed072e4f8">XRTC_INT_MSK_OFFSET</a>&#160;&#160;&#160;0x00000024U</td></tr>
<tr class="memdesc:gac915150ede3fb8aab0d68c1ed072e4f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcIntMsk.  <a href="group__rtcpsu__v1__0.html#gac915150ede3fb8aab0d68c1ed072e4f8">More...</a><br /></td></tr>
<tr class="separator:gac915150ede3fb8aab0d68c1ed072e4f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47db526c5faf75df46c2dc78b84dfb7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga47db526c5faf75df46c2dc78b84dfb7b">XRTC_INT_EN_OFFSET</a>&#160;&#160;&#160;0x00000028U</td></tr>
<tr class="memdesc:ga47db526c5faf75df46c2dc78b84dfb7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcIntEn.  <a href="group__rtcpsu__v1__0.html#ga47db526c5faf75df46c2dc78b84dfb7b">More...</a><br /></td></tr>
<tr class="separator:ga47db526c5faf75df46c2dc78b84dfb7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac41e797cd2c6162d086c237426eafa9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gac41e797cd2c6162d086c237426eafa9e">XRTC_INT_DIS_OFFSET</a>&#160;&#160;&#160;0x0000002CU</td></tr>
<tr class="memdesc:gac41e797cd2c6162d086c237426eafa9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcIntDis.  <a href="group__rtcpsu__v1__0.html#gac41e797cd2c6162d086c237426eafa9e">More...</a><br /></td></tr>
<tr class="separator:gac41e797cd2c6162d086c237426eafa9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36067195ea62374e6d16e333a5cb1ed5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga36067195ea62374e6d16e333a5cb1ed5">XRTC_ADD_ERR_OFFSET</a>&#160;&#160;&#160;0x00000030U</td></tr>
<tr class="memdesc:ga36067195ea62374e6d16e333a5cb1ed5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcAddErr.  <a href="group__rtcpsu__v1__0.html#ga36067195ea62374e6d16e333a5cb1ed5">More...</a><br /></td></tr>
<tr class="separator:ga36067195ea62374e6d16e333a5cb1ed5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa4f868462eb1d1f06c4224696cb43429"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gaa4f868462eb1d1f06c4224696cb43429">XRTC_ADD_ERR_INT_MSK_OFFSET</a>&#160;&#160;&#160;0x00000034U</td></tr>
<tr class="memdesc:gaa4f868462eb1d1f06c4224696cb43429"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcAddErrIntMsk.  <a href="group__rtcpsu__v1__0.html#gaa4f868462eb1d1f06c4224696cb43429">More...</a><br /></td></tr>
<tr class="separator:gaa4f868462eb1d1f06c4224696cb43429"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga795e7dac0dfda7c2cb1f08f27c415d01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga795e7dac0dfda7c2cb1f08f27c415d01">XRTC_ADD_ERR_INT_EN_OFFSET</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:ga795e7dac0dfda7c2cb1f08f27c415d01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcAddErrIntEn.  <a href="group__rtcpsu__v1__0.html#ga795e7dac0dfda7c2cb1f08f27c415d01">More...</a><br /></td></tr>
<tr class="separator:ga795e7dac0dfda7c2cb1f08f27c415d01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga578c0e1d126e0292d9e849afdbff5a6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga578c0e1d126e0292d9e849afdbff5a6a">XRTC_ADD_ERR_INT_DIS_OFFSET</a>&#160;&#160;&#160;0x0000003CU</td></tr>
<tr class="memdesc:ga578c0e1d126e0292d9e849afdbff5a6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcAddErrIntDis.  <a href="group__rtcpsu__v1__0.html#ga578c0e1d126e0292d9e849afdbff5a6a">More...</a><br /></td></tr>
<tr class="separator:ga578c0e1d126e0292d9e849afdbff5a6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0fc893db4a633de94bdfc6f4f59df62f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga0fc893db4a633de94bdfc6f4f59df62f">XRTC_CTL_OFFSET</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga0fc893db4a633de94bdfc6f4f59df62f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcCtl.  <a href="group__rtcpsu__v1__0.html#ga0fc893db4a633de94bdfc6f4f59df62f">More...</a><br /></td></tr>
<tr class="separator:ga0fc893db4a633de94bdfc6f4f59df62f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f92062d8d2cb1c7f0735b1ecd5cdb67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#ga1f92062d8d2cb1c7f0735b1ecd5cdb67">XRTC_SFTY_CHK_OFFSET</a>&#160;&#160;&#160;0x00000050U</td></tr>
<tr class="memdesc:ga1f92062d8d2cb1c7f0735b1ecd5cdb67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcSftyChk.  <a href="group__rtcpsu__v1__0.html#ga1f92062d8d2cb1c7f0735b1ecd5cdb67">More...</a><br /></td></tr>
<tr class="separator:ga1f92062d8d2cb1c7f0735b1ecd5cdb67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7215b93f23fe1ef6cff1004104a803b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gae7215b93f23fe1ef6cff1004104a803b">XRTC_ECO_OFFSET</a>&#160;&#160;&#160;0x00000060U</td></tr>
<tr class="memdesc:gae7215b93f23fe1ef6cff1004104a803b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XrtcEco.  <a href="group__rtcpsu__v1__0.html#gae7215b93f23fe1ef6cff1004104a803b">More...</a><br /></td></tr>
<tr class="separator:gae7215b93f23fe1ef6cff1004104a803b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaccbbc47feabb330a937816bc347766ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gaccbbc47feabb330a937816bc347766ea">XRtcPsu_ReadReg</a>(RegisterAddr)&#160;&#160;&#160;Xil_In32(RegisterAddr)</td></tr>
<tr class="memdesc:gaccbbc47feabb330a937816bc347766ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="group__rtcpsu__v1__0.html#gaccbbc47feabb330a937816bc347766ea">More...</a><br /></td></tr>
<tr class="separator:gaccbbc47feabb330a937816bc347766ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac80374611ede3fc00461df6aaff75028"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtcpsu__v1__0.html#gac80374611ede3fc00461df6aaff75028">XRtcPsu_WriteReg</a>(RegisterAddr,  Data)&#160;&#160;&#160;Xil_Out32(RegisterAddr, (u32)(Data))</td></tr>
<tr class="memdesc:gac80374611ede3fc00461df6aaff75028"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes the given register.  <a href="group__rtcpsu__v1__0.html#gac80374611ede3fc00461df6aaff75028">More...</a><br /></td></tr>
<tr class="separator:gac80374611ede3fc00461df6aaff75028"><td class="memSeparator" colspan="2">&#160;</td></tr>
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